1. Field of the Invention
This invention relates to digital data processing systems of the type having a plurality of memory controllers with interleaved memory units connected to a processing unit by means of a common bus. More particularly, this invention relates to a memory control unit for read and write operations in which the requested word is transferred first with the remaining words serially transferred in ascending modulo four order from/to the memory units.
2. Prior Art
One of the limiting factors in a computer system is the time which is needed to transfer to the processor unit the data stored or to be stored in the memory unit. In order to increase the efficiency of computer systems, it has been recognized that multiple memory word transfers during one memory cycle are advantageous. The problem with multiple memory word transfers centers around the requirement for a large number of parallel data lines with a corresponding increase in the number of pins, wires, drivers, receivers, etc.. It has been found that the physical cost for providing an apparatus of this type becomes prohibitive. In addition, after the multiple memory word transfer has occurred, there is still required an apparatus which selects the requested word from the multiple words received. In has been found desirable to incorporate a selection mechanism which enables the needed word to be first transferred between the processor and memory unit followed serially during the same memory cycle with the rest of the remaining multiple words to be transferred.